This invention relates to systems and techniques that are used to enhance the performance of data communication systems; and more particularly, in one aspect, to enhance the performance of data communication systems (for example, communication systems implemented in wired type environments such as microstrip, stripline, printed circuit board (e.g., a backplane) and cable using receiver based equalization.
Communications systems are continuing to increase the rate at which data is transmitted between devices. The increase in data rate presents a challenge to maintain, enhance or optimize the ability to recover the transmitted signal and thereby the information contained therein. In general, increasing the rate of transfer of data tends to adversely impact the fidelity of the communications.
A technique to address that impact on the communications is to employ equalization circuitry in, for example, the transmitter, receiver, or both the transmitter and receiver. Such circuitry typically “compensates” for the intersymbol interference (ISI) introduced by transmission channel artifacts as well as by modulation, pulse shaping and receiver based circuitry in the communications path. Where the equalization circuitry is implemented in the receiver, it often takes the form of a decision feedback equalization.
Decision feedback equalization employs, among other things, “historical” data samples to compensate for ISI. In this regard, with reference to FIG. 1, in general, typical decision feedback equalization circuitry, after sampling data using a slicer or amplifier and making a decision on the value of the sample, applies the decision to a series of delay stages, each stage having an output that is weighted and summed with the other stages (See, for example, U.S. Pat. No. 4,583,234). The sum is added to the then incoming data. The number of delay stages dictates the amount of “historical” or previous data samples that are incorporated into the feedback to compensate for ISI.
There are many types or implementations of decision feedback equalization. (See, for example, U.S. Pat. Nos. 6,249,544 and 6,252,904, and U.S. patent application Publications 2002/0172276 and 2003/0016770). Conventional decision feedback equalization circuitry is typically quite complicated to implement as well as computationally intensive. As such, the implementation of conventional decision feedback equalization is often difficult and expensive.
There is a need for a system and technique to overcome the shortcomings of one, some or all of the conventional systems, decision feedback equalization circuitry and techniques implementing receiver based equalization circuitry. In this regard, there is a need for an improved decision based equalization circuitry to “compensate” for the intersymbol interference that is less complicated and expensive than conventional circuitry and techniques.